Digital logic : (Record no. 1727)

000 -LEADER
fixed length control field 03958nam a2200301 i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20250225091804.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 250224s2020 ||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781119621638
Qualifying information ebook
040 ## - CATALOGING SOURCE
Transcribing agency uoc
Modifying agency uoc
Description conventions rda
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Edition number 23
Classification number 621.392
Item number RAF
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name RAFIQUZZAMAN, MOHAMED
Relator term author.
9 (RLIN) 4448
245 1# - TITLE STATEMENT
Title Digital logic :
Remainder of title with an introduction to Verilog and FPGA-based design/
Statement of responsibility, etc. Mohamed Rafiquzzaman, Steven A. McNinch
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Hoboken, NJ :
Name of producer, publisher, distributor, manufacturer John Wiley & Sons, Inc., Danvers, MA,
Date of production, publication, distribution, manufacture, or copyright notice 2020
300 ## - PHYSICAL DESCRIPTION
Extent 1 online resource, 444 pages :
Other physical details illustrations; digital, PDF file
336 ## - CONTENT TYPE
Source rdacontent
Content type term text
Content type code txt
337 ## - MEDIA TYPE
Source rdamedia
Media type term computer
Media type code c
338 ## - CARRIER TYPE
Source rdacarrier
Carrier type term online resource
Carrier type code cr
347 ## - DIGITAL FILE CHARACTERISTICS
Source rda
File type text file
Encoding format PDF
500 ## - GENERAL NOTE
General note includes index
520 ## - SUMMARY, ETC.
Summary, etc. Cover -- Title Page -- Copyright -- Contents -- Preface -- Chapter 1: Introduction to Digital Systems -- 1.1 Explanation of Terms -- 1.2 Design Levels -- 1.3 Combinational vs. Sequential Systems -- 1.4 Digital Circuits -- 1.4.1 Diodes -- 1.4.2 Transistors -- 1.4.3 MOS Transistors -- 1.5 Integrated Circuits (ICs -- 1.6 CAD (Computer-Aided Design -- 1.7 Evolution of Digital Logic, Microprocessors, and Microcontrollers -- 1.8 A Typical Application of a Digital System such as a Microcontroller -- Chapter 2: Number Systems, Arithmetic/Logic Operations, and Codes -- 2.1 Number Systems<br/><br/>2.1.1 General Number Representation -- 2.1.2 Converting Numbers from One Base to Another -- 2.2 Unsigned and Signed Binary Numbers -- 2.3 Codes -- 2.3.1 Binary-Coded-Decimal Code (8421 Code -- 2.3.2 Alphanumeric Codes -- 2.3.3 Excess-3 Code -- 2.3.4 Gray Code -- 2.3.5 Unicode -- 2.4 Fixed-Point and Floating-Point Representations -- 2.5 Arithmetic Operations -- 2.5.1 Binary Arithmetic -- 2.5.2 BCD Arithmetic -- 2.5.3 Multiword Binary Addition and Subtraction -- 2.5.4 Binary Multiplication and Division by Shift Operations -- 2.6 Error Correction and Detection -- QUESTIONS AND PROBLEMS<br/><br/>Chapter 3: Digital Logic Gates, Boolean Algebra, and Simplification -- 3.1 Basic Logic Operations -- 3.1.1 NOT Operation -- 3.1.2 OR operation -- 3.1.3 AND operation -- 3.2 Other Logic Operations -- 3.2.1 NOR operation -- 3.2.2 NAND operation -- 3.2.3 Exclusive-OR operation (XOR -- 3.2.4 Exclusive-NOR Operation (XNOR -- 3.3 Positive and Negative Logic -- 3.4 Boolean Algebra -- 3.4.1 Boolean Identities -- 3.4.2 Simplification Using Boolean Identities -- 3.4.3 Consensus Theorem -- 3.4.4 Getting Rid of Glitches or Hazards in Combinational Circuits -- 3.4.5 Complement of a Boolean Function<br/><br/>3.5 XOR / XNOR Implementations -- QUESTIONS AND PROBLEMS -- Chapter 4: Minterms, Maxterms, and Karnaugh Map -- 4.1 Standard Representations -- 4.2 Karnaugh Maps -- 4.2.1 Two-Variable K-map -- 4.2.2 Three-Variable K-map -- 4.2.3 Four-Variable K-map -- 4.2.4 Prime Implicants -- 4.2.5 Expressing a Boolean function in Product-of-sums (POS) form using a K-map -- 4.2.6 Don't Care Conditions -- 4.2.7 Five-Variable K-map -- 4.3 Quine-McCluskey Method -- 4.4 Implementation of Digital Circuits with NAND, and NOR Gates -- 4.4.1 NAND Gate Implementation -- 4.4.2 NOR Gate Implementation<br/><br/>QUESTIONS AND PROBLEMS -- Chapter 5: Analysis and Design of Combinational Circuits Using Gates -- 5.1 Basic Concepts -- 5.2 Analysis of a Combinational Logic Circuit -- 5.3 Design of Combinational Circuits Using Logic Gates -- 5.4 Multiple-Output Combinational Circuits -- QUESTIONS AND PROBLEMS -- Chapter 6: Design of Typical Combinational Logic Components -- 6.1 Design of Typical Combinational Logic Components -- 6.2 Comparators -- 6.3 Decoders -- 6.4 Encoders -- 6.5 Multiplexers -- 6.6 Demultiplexers -- 6.7 Binary Adder/Subtractor and BCD Adder -- QUESTIONS AND PROBLEMS
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element DIGITAL LOGIC
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element VERILOG
9 (RLIN) 1217
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element FPGA
9 (RLIN) 4449
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name McNinch, Steven A.
Relator term author.
9 (RLIN) 4450
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://elibrary.gemzplatform.com/l1sv">https://elibrary.gemzplatform.com/l1sv</a>
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type e-book
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Permanent location Current location Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
          Uofcanada Library Uofcanada Library 02/24/2025   621.392 RAF 00010063 02/24/2025 02/24/2025 e-book

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